As memory devices become highly integrated, it is necessary to decrease the size of circuit components. One way to retain the storage capacity of a dynamic random access memory (DRAM) device and decrease its size is to increase the dielectric constant of the dielectric layer of the storage cell capacitor. In order to achieve the charge storage efficiency needed in 256 megabit(Mb) memories and above, materials having a high dielectric constant, typically greater than 50, can be used as the dielectric layer between the storage node electrode (a lower capacitor electrode) and the cell plate capacitor electrode (an upper capacitor electrode). The dielectric constant is a value characteristic of a material and is proportional to the amount of charge that can be stored in the material when it is interposed between two electrodes. Among several high dielectric constant materials, particularly, (Ba, Sr)TiO.sub.3 [BST] material is mainly used in highly integrated semiconductor circuit devices. Since the BST film has a high dielectric constant between about 200 and 300 in accordance with its fabricating process, capacitors using the BST film can respectively obtain a desired capacitance value.
Unfortunately, the BST material is incompatible with existing processes and can not be simply deposited on a polysilicon electrode, unlike the other dielectric materials, such as Si.sub.3 N.sub.4 and SiO.sub.2 /Si.sub.3 N.sub.4 composite layers. This incompatibility is a result of the O.sub.2 rich ambient present during the high dielectric constant material deposition or during annealing steps. The O.sub.2 oxidizes portions of the materials formerly used for the storage node plate. Also, the capacitors employing BST undergo physical degradation during thermal cycles due to the diffusion of the cell plate material into the dielectric.
In the storage cell capacitor incorporating BST, some of these problems are resolved. The storage node electrode typically comprises a layer of platinum overlying a reaction barrier layer which, in turn, overlies a polysilicon plug. Platinum is used as the upper portion of the first electrode since it will not oxidize during a BST deposition or subsequent annealing steps. An electrode that oxidizes would have a low dielectric constant film below the BST, thereby negating the advantages provided by the high dielectric constant material. The reaction barrier layer, e.g., constructed of titanium nitride or tantalum is introduced to avoid Si and Pt inter-diffusion and to prevent the formation of SiO.sub.2 on top of the platinum surface. In addition, the reaction barrier layer protects the top surface thereof from strong oxidizing conditions during the BST deposition. FIG. 1 depicts the stacked storage node electrode of the related art comprising reaction barrier layer 1, platinum storage node electrode 2 (Ta/Pt) overlying the polysilicon plug 3.
However, the sidewalls 4 of the reaction barrier layer 1 formed during this process are subject to oxidation during the subsequent deposition of the BST layer (not shown in FIG. 1). Since the reaction barrier layer 1 oxidizes, the polysilicon plug 3 is also susceptible to oxidation. When portions of the polysilicon plug 3 and the material of the reaction barrier layer 1 are oxidized, the capacitance of the storage cell capacitor is decreased since the storage node electrode is partially covered by a low dielectric constant film formed due to the partial oxidation of the storage node electrode. This capacitance reduction leads to increase in leakage current.
In addition, during the high dielectric constant material deposition or during annealing steps, O.sub.2 is penetrated into the platinum storage node electrode 2 through grain boundaries thereof, thereby oxidizing the surface of the polysilicon plug 3, and the platinum itself reacts to the polysilicon, thereby forming a silicide composite film therebetween.
Furthermore, the storage node contact resistance increases drastically between the polysilicon plug 3 and the reaction barrier layer 1 as a result of degradation of the reaction barrier layer during deposition of BST and other high dielectric constant materials.
Subsequently, as shown in FIG. 1B, a thin film 6 of BST material is provided over the platinum layer 2, and finally the cell plate capacitor electrode serving as an upper capacitor electrode 7 is formed on the BST film 6. As a result, the prior art storage cell capacitor is completed.
An ideal capacitor construction is illustrated in FIG. 1B, although such construction may not practically occur during the fabrication of a capacitor. Specifically, with reference to FIG. 1C, the sidewalls 4 of the reaction barrier layer 1 is oxidized, thereby resulting in formation of a wedge-shaped oxide layer 8. This actually creates stresses and cracks where the wedge-shaped oxide layer 8, as shown in FIG. 1C, is formed.
Thus, the process for minimizing partial oxidation of a reaction barrier layer and decreasing contact resistance between a polysilicon plug and the reaction barrier layer is disclosed in U.S. Pat. No. 5,381,302. In this process, as shown in FIG. 2, the storage cell capacitor features a storage node electrode having a reaction barrier layer which prohibits diffusion of atoms. The reaction barrier layer may be titanium nitride or another material which prohibits silicon diffusion. The reaction barrier layer is interposed between a conductive plug 13 and a non-oxidizing conductive material 12 such as platinum. A dielectric layer 17, typically BST, is deposited on the non-oxidizing material 12. The reaction barrier layer is surrounded on its sides by an insulating layer 15. The reaction barrier layer is comprised of two layers: a first barrier layer 16 such as titanium silicide and a second barrier layer 11 such as titanium nitride.
The prior art capacitor forming method illustrated in FIG. 2 can prevent a wedge-shaped oxide layer from being formed as shown in FIG. 1C during the deposition of BST or subsequent annealing steps, but has still another problem. Since the platinum layer 12 is patterned only by a dry etching process using an electrode forming mask while etched, the method illustrated in FIG. 2 as well as the method illustrated in FIGS. 1A to 1C can not be applicable to fabrication of semiconductor memory devices with small design rule, i.e., high integration degree. This method of forming platinum capacitor electrode is illustrated in FIGS. 3A to 3C.
Referring to FIG. 3A, a layer 23 of, for example, TiN material is provided over a conductive plug 21 which is defined by an insulating layer 22 on a semiconductor substrate 20. A platinum layer 24 is provided over the TiN layer 23, which serves as a reaction barrier layer, and then photoresist mask 26 is provided on the platinum layer 24 so as to form a lower capacitor electrode. Subsequently, when a dry etching process using the mask 26 is carried out to achieve the platinum layer patterns 24, part of sputtered platinum particles 28 is adhered to sidewalls of the mask 26, and thereby the mask 26 has a profile shown in FIG. 3B. As is apparent from FIG. 3B, since the sputtered platinum particles 28 adhere more to the lower portions of the mask sidewalls than to the upper portions thereof, the bottom portion of the mask 26 becomes wider. The dry etching process using the mask whose bottom portion is wider continues to be carried out to form platinum patterns having slackly inclined plans as shown in FIG. 3C.
As described above, when the prior art method of forming capacitors is applied to highly integrated semiconductor memory devices, there arises a need for a method of insuring that the platinum patterns are electrically separated from one another.